This application claims priority from Korean Priority Document No. 99-20445, filed on Jun. 3, 1999, and 99-22498, filed on Jun. 16, 1999, both with the Korean Industrial Property Office, which documents are hereby incorporated by reference.
This invention relates to semiconductor devices. More particularly, the invention relates to a redundancy selection circuit of a flash memory device and a method of using same that allows testing for defective redundant memory cells.
Generally, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices lose their data at power-off, while the nonvolatile semiconductor memory devices maintain their data even at power-off. Therefore, the nonvolatile semiconductor memory devices have been widely used in applications in which power can be interrupted suddenly.
A nonvolatile semiconductor memory device, such as a flash memory device, comprises electrically erasable and programmable ROM cells, each of which is referred to as xe2x80x9ca flash EEPROM cellxe2x80x9d. The flash EEPROM cell includes a cell transistor. As illustrated in FIG. 1, the cell transistor has a semiconductor substrate (or bulk) 2 of a first conductive type (e.g., P-type), and source and drain regions 3 and 4 of a second conductive type (e.g., N-type) spaced from each other. A floating gate 5 for storing charges is placed over a channel region between the source and drain regions 3 and 4, and a control gate 6 placed over the floating gate 5. Gate 5 is understood to have a floating voltage potential. Other structure around it is not shown.
Programming of the flash EEPROM cell is carried out by a hot carrier injection mechanism. The hot carrier injection is performed by applying a high voltage (e.g., +10V) to its control gate 6 and an appropriate positive voltage (e.g., +5V-+6V) to its drain at the drain terminal Vd. At this time, the bulk 2 of the EEPROM cell transistor is grounded, along with the source, by grounding the source terminal Vs. According to this bias condition of the flash EEPROM cell, hot charge carriers are injected to the floating gate 5 from the channel region adjacent to the drain 4, and thereby the threshold voltage of the EEPROM cell transistor is shifted into a target threshold voltage range for a programmed cell transistor (e.g., 6V-7V).
Erasing of the flash EEPROM cell is carried out by a Fowler-Nordheim (F-N) tunneling mechanism. The F-N tunneling is performed by applying a negative high voltage (e.g., xe2x88x9210V) to its control gate 6 and an appropriate positive voltage (e.g., +5V) to its bulk 2. At this time, its source and drain remain at a high-impedance (or floating) state. According to this bias condition, negative electrons in the floating gate 5 are discharged into the source 3 or into the bulk 2, and thereby the threshold voltage is shifted into a target threshold voltage range for an erased cell transistor (e.g., 1V-3V). The target threshold voltage distributions of the programmed and erased EEPROM cell transistors are illustrated in FIG. 2.
Reading of the EEPROM cell transistor is carried out by applying a voltage of 4.5V to its gate 6, and a voltage of 1V to its drain 4. During reading, its source 3 and bulk 2 are grounded. According to this bias condition, the programmed EEPROM cell transistor conducts no current from its drain 4 to its source 3, and is referred to as an xe2x80x9cOFFxe2x80x9d cell. On the other hand, the erased EEPROM cell transistor conducts current from its drain 4 to its source 3, and is referred to as an xe2x80x9cONxe2x80x9d cell.
The flash memory device includes an array of the flash EEPROM cells arranged along rows and columns, which are arranged orthogonally to each other. The density of defects generated in such a flash memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on the semiconductor manufacturing technology. The higher the integration density of the device, the greater is the ratio of the number of normal memory cells to that of defective memory cells. Even if the device, however, includes only one defective memory cell therein, the device cannot operate normally, and therefore, the device is abandoned (discarded). This limits the manufacturing yield.
In order to be able to operate the flash memory device in spite of such defective memory cells, a redundant cell array is incorporated in the flash memory device along with the main cell array. In a flash memory device incorporating such a redundant cell array, the manufacturing yield can be improved.
Referring to FIG. 3, a conventional flash memory device includes a main cell array 10 with a plurality of first columns of main memory cells and a redundant cell array 20 with a plurality of second columns of redundant memory cells. Furthermore, the flash memory device includes a circuit 30 for replacing a first column of at least one defective memory cell (or a defective column of main memory cells) with a second column of redundant memory cells. Hereinafter, such a circuit 30 is named xe2x80x9ca redundancy selection circuitxe2x80x9d.
As illustrated in FIG. 3, an address storage block 32 and an input/output coding block 34 constitute the redundancy selection circuit 30. The address storage block 32 stores column addresses for defective columns so that a defective column in the main cell array 10 can be replaced with a redundant column in the redundant cell array 20 by use of fuse elements (e.g., electrical fuses or laser beam fuses). The input/output coding block 34 generates redundancy selection signals RSi in response to output signals from the address storage block 32. The redundancy selection signals RSi correspond to input/output pins I/O (in this embodiment, i=0-15) of the flash memory device, respectively.
During reading, a column pass gate circuit 40 responds to output signals from a column decoder circuit 50 and selects a part of first columns in the main cell array 10 and at least one of second columns in the redundant cell array 20. The selected columns of the main cell array 10 correspond to the input/output pins I/O0-I/O15, respectively. Simultaneously, a row address decoder 60 decodes row addresses RA into signals WL0, . . . , WLm.
Then a sense amplifier SA and write driver WD circuit 70 reads out data from the main cell array 10 via the selected columns. A sense amplifier and write driver circuit 80 reads out data from the redundant cell array 20 via the selected column. If the column address CA inputted in block 32 equals a stored address in the address storage block 32, one of the redundancy selection signals RSi is activated. This happens because one of the selected columns in the main cell array 10 is defective. Therefore, a multiplexer circuit 90 responds to the activated redundancy selection signal RSi, and selects data read out via the selected column of the redundant cell array 20, instead of data read out via the defective column of the main cell array 10. An I/O buffer 100 outputs the data from multiplexer 90.
A problem arises when the address storage block 32 stores addresses for defective columns by cutting electrical or laser beam fuses incorporated in the blocks 32 and 34 at a wafer level or at a package level. This problem is that it is impossible to test all redundant memory cells in the redundant cell array 20 for defects. In order to solve this drawback, additional circuitry has been used for enabling the redundant memory cells to be estimated. However, the additional circuitry occupies space, which makes the size of the flash memory device increase. Furthermore, cutting the fuses of the redundancy selection circuit 30 takes a long time.
It is therefore an object of the invention to provide a flash memory device with a redundancy selection circuit, which is capable of testing all redundant memory cells for defects, without limitation.
It is another object of the invention to provide a flash memory device with a redundancy selection circuit, which is capable of reducing test time.
In accordance with one aspect of the present invention, a flash memory device is provided, and a method of using the same.
The flash memory device of the invention includes a main cell array divided into plural input/output blocks, each of which corresponds to the input/output pins and has a bit segment of plural main columns of main memory cells, and a redundancy cell array including a redundant bit segment of plural redundant columns of redundant memory cells. The device also includes a column selector for selecting at least two of the main columns and at least one of the redundant columns in response to a column address. The device additionally includes a plurality of first sense amplifiers each corresponding to the input/output blocks, each for sensing and amplifying stored data in a corresponding input/output block via a corresponding main column thus selected, and at least one second sense amplifier for sensing and amplifying stored data in the redundant cell array via the redundant column thus selected. A plurality of multiplexers are coupled to the input/output pins, each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier, and for selecting one of the outputs thus received in response to a corresponding one of the redundancy selection signals.
An important part of the invention is a redundancy selection circuit for generating redundancy selection signals, each corresponding to the input/output pins in response to the column address. The redundancy selection circuit includes generation means for simultaneously generating a first redundancy address and a second redundancy address in response to the column address at a read cycle. The first redundancy address indicates whether the column indexed by the column address is defective, and the second redundancy address indicates the place where a defective one of the selected main columns is positioned. The device also includes means for generating the redundancy selection signals in response to the first and second redundancy addresses.
In this embodiment, the flash memory device can perform a test mode of operation in which all the redundant memory cells are tested for defectiveness.
In this embodiment, during the test mode of operation, test addresses are programmed in the generating means such that data on the selected redundant column is outputted at a read cycle of the test mode of operation, regardless of whether defective memory cells exist in the main cell array.
In this embodiment, the generating means comprises an array of a plurality of cell units, each of which includes at least two memory cells that are the same as the main memory cells. Each of the memory cells comprises an electrically erasable and programmable read-only memory (EEPROM) cell, which includes a cell transistor having a source, a drain, a floating gate and a control gate. The gates are connected in common to a word line in the generating means, the drains of the two EEPROM cells are connected in common to a corresponding bit line in the generating means, and the sources of the two EEPROM cells are connected to a source line in the generating means.
In this embodiment, the generating means further includes a decoder for generating selection signals in response to the column address; a second column selector for selecting a part of the bit lines in the generating means in response to the selection signals; and a plurality of third sense amplifiers, each for reading out a data bit signal from the array in the generating means via the selected bit line. The data bit signals that read out by the third sense amplifiers are outputted as the first and second redundancy addresses.
A method according to the invention is to place the flash memory device in a test mode, and testing the main cells. Then a plurality of column addresses is sequentially generated, for each of the redundancy columns. The column addresses are applied to a redundancy selection circuit, which generates redundancy selection signals. The redundancy selection signals are applied to a plurality of multiplexers to select a redundancy column. Then all the redundant cells in the selected redundancy column are tested.